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Seeing through hardware counters: a journey to threefold performance increase

The Netflix TechBlog

By Vadim Filanovsky and Harshad Sane In one of our previous blogposts, A Microscope on Microservices we outlined three broad domains of observability (or “levels of magnification,” as we referred to them)?—?Fleet-wide, Fleet-wide, Microservice and Instance.

Hardware 285
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SQL Server Hardware Optimization

SQL Server Performance

An important concern in optimizing the hardware platform is hardware components that restrict performance, known as bottlenecks. General DBA Performance Tuning hardwareQuite often, the problem isn’t correcting performance bottlenecks as much as it is identifying them in the first place. Start with obtaining a performance baseline. You monitor the server over time so that you can determine Server average […].

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SQL Server Hardware Performance Tuning

SQL Shack

SQL Server Performance Tuning can be a difficult assignment, especially when working with a massive database where even the minor change can raise a significant impact on the existing query performance.

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Implementing U2F Authentication With Hardware Keys Using Node.js and Vue.js

The Polyglot Developer

and jQuery , which demonstrated how to use hardware keys as a means of universal two-factor (U2F) authentication. The post Implementing U2F Authentication With Hardware Keys Using Node.js Not too long ago I had written a tutorial titled, U2F Authentication with a YubiKey Using Node.js

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Create A Bitcoin Hardware Wallet With Golang And A Raspberry Pi Zero

The Polyglot Developer

Over the past month or so, in my free time, I’ve been working towards creating an affordable hardware wallet for various cryptocurrencies such as Bitcoin. The post Create A Bitcoin Hardware Wallet With Golang And A Raspberry Pi Zero appeared first on The Polyglot Developer

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An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems

The Morning Paper

An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems Gan et al., The paper examines the implications of microservices at the hardware, OS and networking stack, cluster management, and application framework levels, as well as the impact of tail latency. Hardware implications. ASPLOS’19.

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Using hardware performance counters to determine how often both logical processors are active on an Intel CPU

John McCalpin

Most Intel microprocessors support “HyperThreading” (Intel’s trademark for their implementation of “simultaneous multithreading”) — which allows the hardware to support (typically) two “Logical Processors” for each physical core. Last year I was trying to diagnose a mild slowdown in a code, and wanted to be able to use the hardware performance counters to divide processor activity into four categories: Neither Logical Processor active.

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SKP's Java/Java EE Gotchas: Clash of the Titans, C++ vs. Java!

DZone

performance c++ programming languages core java computing computer hardware programming & design complexity metrics optimization and algorithmic aspects platform independenceAs a Software Engineer, the mind is trained to seek optimizations in every aspect of development and ooze out every bit of available CPU Resource to deliver a performing application.

Java 167
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Achieving 100Gbps intrusion prevention on a single server

The Morning Paper

So we need low latency, but we also need very high throughput: A recurring theme in IDS/IPS literature is the gap between the workloads they need to handle and the capabilities of existing hardware/software implementations. Uncategorized Hardware Networking

Servers 103
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Benchmarking the AWS Graviton2 with KeyDB

DZone

database big data performance benchmarking performance analysis redis alternative ec2 image ec2stack hardware news keydbWe've always been excited about Arm so when Amazon offered us early access to their new Arm-based instances we jumped at the chance to see what they could do.

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Identifying Optane drives in Linux

n0derunner

Storage Hardware and Devices nvme optaneThe easiest way to identify NVME drives backed by either NAND flash or Optane is to use $ lspci -v The output will look like this for NVME/NAND 00:0d.0

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A Brief Guide of xPU for AI Accelerators

ACM Sigarch

HPU: Holographic Processing Unit (HPU) is the specific hardware of Microsoft’s Hololens. SPU: Stream Processing Unit (SPU) is related to the specialized hardware to process the data streams of video. TPU: Tensor Processing Unit (TPU) is Google’s specialized hardware for neural network. Movidius, which was acquired by Intel in 2016, develops its VPU-series named Myriad which makes hardware optimization for computer vision tasks.

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Peloton: Uber’s Unified Resource Scheduler for Diverse Cluster Workloads

Uber Engineering

Cluster management, a common software infrastructure among technology companies, aggregates compute resources from a collection of physical hosts into a shared resource pool, amplifying compute power and allowing for the flexible use of data center hardware. Architecture Apache Hadoop Apache Spark Big Data Capacity Planning Cassandra Cluster Management Data Center Hardware MySQL Peloton Redis Uber Uber Engineering Unified Resource Scheduler Workload Cluster

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Using Machine Learning to Ensure the Capacity Safety of Individual Microservices

Uber Engineering

Architecture Capacity Capacity Safety Hardware Capacity Planning Reliability site reliability engineering SRE Uber Eng Uber EngineeringReliability engineering teams at Uber build the tools, libraries, and infrastructure that enable engineers to operate our thousands of microservices reliably at scale.

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An empirical guide to the behavior and use of scalable persistent memory

The Morning Paper

EWR is the ratio of bytes issue by the iMC divided by the number of bytes actually written to the 3D-XPoint media (as measured by the DIMM’s hardware counters). Uncategorized Hardware PerformanceAn empirical guide to the behavior and use of scalable persistent memory , Yang et al.,

Latency 56
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Compress objects, not cache lines: an object-based compressed memory hierarchy

The Morning Paper

… to realize these insights, hardware needs to access data at object granularity and must have control over pointers between objects. Hotpads is a hardware-managed hierarchy of scratchpad-like memories called pads. Collection evictions that move objects up the hierarchy occur entirely in hardware and are much faster than software GT because pads are small. Uncategorized Hardware Operating Systems

Cache 54
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A persistent problem: managing pointers in NVM

The Morning Paper

Byte-addressable non-volatile memory,) NVM will fundamentally change the way hardware interacts, the way operating systems are designed, and the way applications operate on data. " Uncategorized Hardware Operating SystemsA persistent problem: managing pointers in NVM Bittman et al.,

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Efficient lock-free durable sets

The Morning Paper

Uncategorized Algorithms and data structures HardwareEfficient lock-free durable sets Zuriel et al., OOPSLA’19. Given non-volatile memory (NVRAM), the naive hope for persistence is that it would be a no-op: what happens in memory, stays in memory.

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Peloton: Uber’s Unified Resource Scheduler for Diverse Cluster Workloads

Uber Engineering

Cluster management, a common software infrastructure among technology companies, aggregates compute resources from a collection of physical hosts into a shared resource pool, amplifying compute power and allowing for the flexible use of data center hardware. Architecture Apache Hadoop Apache Spark Big Data Capacity Planning Cassandra Cluster Management Data Center Hardware MySQL Peloton Redis Uber Uber Engineering Unified Resource Scheduler Workload Cluster

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Approaches to System Security: Using Cryptographic Techniques to Minimize Trust

ACM Sigarch

This is the first post in a series of posts on different approaches to systems security especially as they apply to hardware and architectural security. The class of techniques described in this blog post, which we broadly refer to as applied hardware and architecture cryptography, apply proven cryptographic techniques to strengthen systems. Naively securing this system would require a large amount of trust; “guns and guards”, trusted personnel, and trusted software and hardware.

Systems 44
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How to Migrate Redis™ Data Using Redis-Shake

Scalegrid

Two of the main reasons we hear are often due to migration of hardware, or the need to split data between servers. Migrating ScaleGrid for Redis™ data from one server to another is a common requirement that we hear from our customers.

Hardware 178
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Why I hate MPI (from a performance analysis perspective)

John McCalpin

According to Dr. Bandwidth, performance analysis has two recurring themes: How fast should this code (or “simple” variations on this code) run on this hardware? This can start with either a “top-down” or “bottom-up” approach, but in complex codes running on complex hardware, what is really required is both approaches — iterated until the interactions between all the components are understood. The networking hardware.

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Boosted race trees for low energy classification

The Morning Paper

The goal is to produce a low-energy hardware classifier for embedded applications doing local processing of sensor data. Race logic has four primary operations that are easy to implement in hardware: MAX, MIN, ADD-CONSTANT, and INHIBIT. One efficient way of doing that in analog hardware is the use of current-starved inverters. Uncategorized Hardware Machine LearningBoosted race trees for low energy classification Tzimpragos et al., ASPLOS’19.

Energy 48
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James Hamilton on reliability

Sutter's Mill

Don’t trust hardware or software; then you can build trustworthy hardware and software. Hardware Software DevelopmentJames Hamilton on how to write reliable software in a world where anything that can fail, will fail.

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Containerizing the Beast – Hadoop NameNodes in Uber’s Infrastructure

Uber Engineering

We recently containerized Hadoop NameNodes and upgraded hardware, improving NameNode RPC queue time from ~200 to ~20ms – A 10x improvement! With this radical change, Uber’s Hadoop customers are happier and admins rest more at night. Data / ML

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Invited Talk at SuperComputing 2016!

John McCalpin

Computer Architecture Computer Hardware Performance cache DRAM high performance computing memory bandwidth memory latency STREAM benchmark“Memory Bandwidth and System Balance in HPC Systems” If you are planning to attend the SuperComputing 2016 conference in Salt Lake City next month, be sure to reserve a spot on your calendar for my talk on Wednesday afternoon (4:15pm-5:00pm).

Systems 40
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A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing)

John McCalpin

Hardware performance counter results for a simple benchmark code calling Intel’s optimized DGEMM implementation for this processor (from the Intel MKL library) show that about 20% of the dynamic instruction count consists of instructions that are not packed SIMD operations (i.e., This is an uninspiring fraction of peak performance that would normally suggest significant inefficiencies in either the hardware or software.

Latency 40
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Intel discloses “vector+SIMD” instructions for future processors

John McCalpin

It seems very likely that the hardware has to be able to merge these two load operations into a single L1 Data Cache access to keep the rate of cache accesses from being the performance bottleneck. But 2 32-bit loads is only 1/8 of a natural 512-bit cache access, and it seems unlikely that the hardware can merge cache accesses across multiple cycles. Algorithms Computer Architecture Computer Hardware Performance arithmetic high performance computing microprocessors

Cache 40
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Memory Latency on the Intel Xeon Phi x200 “Knights Landing” processor

John McCalpin

Cache Coherence Implementations Computer Architecture Computer Hardware Performance memory bandwidth memory latency Xeon PhiThe Xeon Phi x200 (Knights Landing) has a lot of modes of operation (selected at boot time), and the latency and bandwidth characteristics are slightly different for each mode.

Latency 40
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Monitoring Web Servers Should Never Be Complex

DZone

For example, you can monitor the behavior of your applications, the hardware usage of your server nodes, or even the network traffic between servers. One prominent solution is the open-source tool Nagios which allows you to monitor hardware in every detail. Introduction.

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Beginners’ Guide to Run a Linux Server Securely

DZone

Imagine you can benefit from an up-to-date and fully-loaded operating system on a 90s hardware configuration of 512 MB and 1-core CPU. Linux could be a fantastic choice for your next cloud server.

Servers 157
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Building Resiliency With Effective Error Management

DZone

Hardware - servers/storage hardware/software faults such as disk failure, disk full, other hardware failures, servers running out of allocated resources, server software behaving abnormally, intra DC network connectivity issues, etc.

Hardware 205
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Software AI Accelerators: AI Performance Boost for Free

DZone

This has not only led to AI acceleration being incorporated into common chip architectures such as CPUs, GPUs, and FPGAs but also mushroomed a class of dedicated hardware AI accelerators specifically designed to accelerate artificial neural networks and machine learning applications.

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From bare-metal to Kubernetes

High Scalability

Hardware infrastructure. This is a guest post by Hugues Alary , Lead Engineer at Betabrand , a retail clothing company and crowdfunding platform, based in San Francisco. This article was originally published here. Early infrastructure. Rackspace. The scalability and maintainability issue. Scaling development processes. The advent of Docker. Kubernetes. Learning Kubernetes. Officially migrating. The development/staging environments. A year after. kubernetes

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Talk Video: Welcome to the Jungle

Sutter's Mill

Now welcome to the hardware jungle. Concurrency Hardware Software Development Talks & Events WebLast month in Kansas City I gave a talk on “Welcome to the Jungle,” based on my recent essay of the same name (sequel to “The Free Lunch Is Over”) concerning the turn to mainstream heterogeneous distributed computing and the end of Moore’s Law.

Cloud 40
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Security of Quantum Computer Architectures

ACM Sigarch

Otherwise, there is a risk of repeating many of the mistakes from classical computers where, for many years, security at the hardware and architecture levels was an afterthought. Hardware Security Aspects of Quantum Computer Architectures. Introduction.

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FIDO Authentication in Percona Server for MySQL 8.0.30-22

Percona

With this new plugin, it is possible to perform multi-factor authentication using hardware keys, or single-factor passwordless authentication with the same keys. Percona Server for MySQL 8.0.30-22 introduces a new authentication plugin, named authentication_fido.

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Distributed Network Service for Users Activity Limiting (Part 1)

DZone

But what is the metric that shows service hardware monopolization by a group of users? Scenario. Any service provider tries to reach several metrics in their activity. One group of these metrics is service quality. Quality metrics contain: The ratio of successfully processed requests.

Network 207
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Keynote at the AMD Fusion Developer Summit

Sutter's Mill

We know that getting full computational performance out of most machines—nearly all desktops and laptops, most game consoles, and the newest smartphones—already means harnessing local parallel hardware, mainly in the form of multicore CPU processing. You can expect the above keynote to be, well, keynote-y… oriented toward software product features and of course AMD’s hardware, with plenty of forward-looking industry vision style material.

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Welcome to the Jungle

Sutter's Mill

Now welcome to the hardware jungle. For the first time in the history of computing, mainstream hardware is no longer a single-processor von Neumann machine, and never will be again. Concurrency Hardware Opinion & Editorial Software DevelopmentWith so much happening in the computing world, now seemed like the right time to write “Welcome to the Jungle” – a sequel to my earlier “The Free Lunch Is Over” essay. Here’s the introduction: Welcome to the Jungle.

Games 40
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Adaptive Loading - Improving web performance on low-end devices

Addy Osmani

Adaptive Loading is a pattern for delivering a fast core experience to all users (including low-end devices) where you progressively add high-end-only features, if a user's network and hardware can handle it

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Two Sessions: C++ Concurrency and Parallelism – 2012 State of the Art (and Standard)

Sutter's Mill

Mainstream hardware – many kinds of parallelism: What’s the relationship among multi-core CPUs, hardware threads , SIMD vector units (Intel SSE and AVX , ARM Neon ), and GPGPU (general-purpose computation on GPUs, which I covered at C++ and Beyond 2011 )? Task and data parallelism: What’s the difference between task parallelism and data parallelism, which kind of of hardware does each allow you to exploit, and why?

C++ 40
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3 Trends in Artificial Intelligence and Machine Learning for 2023

DZone

The need for automation in the enterprise, coupled with advances in AI/ML hardware and software, is making the application of these technologies a reality