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Kubernetes in the wild report 2023

Dynatrace

The report also reveals the leading programming languages practitioners use for application workloads. are the top 3 programming languages for Kubernetes application workloads. Of the organizations in the Kubernetes survey, 71% run databases and caches in Kubernetes, representing a +48% year-over-year increase.

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Geek Reading - Week of June 5, 2013

DZone

These items are a combination of tech business news, development news and programming tools and techniques. Simpler UI Testing with CasperJS ( Architects Zone – Architectural Design Patterns & Best Practices). Using MongoDB as a cache store ( Architects Zone – Architectural Design Patterns & Best Practices).

Java 244
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Dynatrace supports SnapStart for Lambda as an AWS launch partner

Dynatrace

Today, application modernization efforts are centered on application programming interfaces and microservices that are sensitive to startup latency. Lambda then takes a snapshot of the memory and disk state of the initialized execution environment, persists the encrypted snapshot, and caches it for low-latency access.

Lambda 218
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Architectural Myopia

ACM Sigarch

It is much more difficult to publish truly risky, revolutionary research due to implicit filters in what gets funded and what makes it past a program committee. I had a professor in grad school who used to joke that all architecture is reinvented every 5 years. However, a similar near term bias exists in academia. Discounting the Past.

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Current status, needs, and challenges in Heterogeneous and Composable Memory from the HCM workshop (HPCA’23)

ACM Sigarch

Introduction Memory systems are evolving into heterogeneous and composable architectures. using Compute Express Link or CXL), organizing memory components for optimal performance, adapting system software traditionally designed for homogeneous memory systems, and developing memory abstractions and programming constructs for HCM management.

Latency 52
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Predictive CPU isolation of containers at Netflix

The Netflix TechBlog

Because microprocessors are so fast, computer architecture design has evolved towards adding various levels of caching between compute units and the main memory, in order to hide the latency of bringing the bits to the brains. This avoids thrashing caches too much for B and evens out the pressure on the L3 caches of the machine.

Cache 251
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USENIX SREcon APAC 2022: Computing Performance: What's on the Horizon

Brendan Gregg

I'm now program co-chair for SREcon 2023 APAC, and our 2023 conference is June 14-16 in Singapore. And now, helping bring USENIX conferences to Australia by giving the first keynote: I could not have scripted or expected it. The call for participation ends on March 2nd 23:59 SGT!