Dynatrace

AUGUST 30, 2019

Reducing CPU Utilization to now only consume 15% of initially provisioned hardware. Missing Cache Settings – Make sure you cache resources that don’t change often on the browser or use a CDN. Reducing performance and architectural issues in their backend system gave them a 99% performance improvement!

Cache 201

Cache Database Architecture Government 201

The Netflix TechBlog

JUNE 4, 2019

Because microprocessors are so fast, computer architecture design has evolved towards adding various levels of caching between compute units and the main memory, in order to hide the latency of bringing the bits to the brains. This avoids thrashing caches too much for B and evens out the pressure on the L3 caches of the machine.

Cache 251

Cache Latency Airlines Logistics 251

ACM Sigarch

FEBRUARY 23, 2018

I had a professor in grad school who used to joke that all architecture is reinvented every 5 years. Both virtualization and power burst onto the architecture community seemingly out of nowhere even though there was a clear historical basis and trend for both. We believed existing hardware and OS protocols protected the processor.

Architecture 47

Architecture Cache Hardware Virtualization 47

ACM Sigarch

MAY 31, 2023

Introduction Memory systems are evolving into heterogeneous and composable architectures. There are three common mechanisms to access remote memory: modifying applications, modifying virtual memory, and hardware-level cache coherence support. About CXL hardware availability with academia. Using emulation (e.g.

Latency 52

Latency Hardware Cache Architecture 52

Percona

JUNE 22, 2023

Defining high availability In general terms, high availability refers to the continuous operation of a system with little to no interruption to end users in the event of hardware or software failures, power outages, or other disruptions. If a primary server fails, a backup server can take over and continue to serve requests.

Availability 104

Availability Database Open Source Hardware 104

The Morning Paper

MAY 12, 2019

An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems Gan et al., A typical architecture diagram for one of these services looks like this: Suitably armed with a set of benchmark microservices applications, the investigation can begin! Hardware implications.

Open Source 61

Open Source Hardware Benchmarking Systems 61

Scalegrid

DECEMBER 21, 2023

With its widespread use in modern application architectures, understanding the ins and outs of Redis® monitoring is essential for any tech professional. To monitor Redis® instances effectively, collect Redis metrics focusing on cache hit ratio, memory allocated, and latency threshold.

Strategy 130

Strategy Monitoring Latency DevOps 130

ACM Sigarch

OCTOBER 12, 2020

The focus of most published research in architecture is on applications implemented in high-performance, “ close-to-the-metal” languages essentially developed before computers got fast. Are caches large enough for this code? There’s some work on hardware proposals for these systems, like Zhu et al.,

C++ 108

C++ Benchmarking Hardware Architecture 108

High Scalability

NOVEMBER 25, 2019

Over time, costs for S3 and GCS became reasonable and with Egnyte’s storage plugin architecture, our customers can now bring in any storage backend of their choice. Edge caching. In general, Egnyte connect architecture shards and caches data at different levels based on: Amount of data. Nginx for disk based caching.

Architecture 52

Architecture Cache Azure Storage 52

The Morning Paper

MARCH 8, 2020

When I think about cloud-native architectures, I think about disaggregation (enabling each resource type to scale independently), fine-grained units of resource allocation (enabling rapid response to changing workload demands, i.e. elasticity), and isolation (keeping tenants apart). From shared-nothing to disaggregation.

Storage 112

Storage Engineering Cache Serverless 112

ACM Sigarch

JULY 17, 2023

An example of a specification is the correct operation of the hardware of a microprocessor. An SDC is the worst possible outcome of a fault, as it can have an arbitrary impact on the correctness of software running on the hardware. Vilas Sridharan is an AMD Senior Fellow and leads the RAS Architecture team. All rights reserved.

Energy 52

Energy Hardware Best Practices Architecture 52

Scalegrid

JANUARY 5, 2024

These can be mitigated through the implementation of: efficient query optimization caching of database queries utilization of database indexes implementation of session storage employing database read replication and sharding.

Efficiency 147

Efficiency Storage Database Scalability 147

Brendan Gregg

FEBRUARY 28, 2023

Make sure your system can handle next-generation DRAM,” [link] Nov 2011 - [Hruska 12] Joel Hruska, “The future of CPU scaling: Exploring options on the cutting edge,” [link] Feb 2012 - [Gregg 13] Brendan Gregg, “Blazing Performance with Flame Graphs,” [link] 2013 - [Shimpi 13] Anand Lal Shimpi, “Seagate to Ship 5TB HDD in 2014 using Shingled Magnetic (..)

Performance 110

Performance Latency Cache Virtualization 110

The Morning Paper

APRIL 14, 2019

The paper sets out what we can do in software given today’s hardware, and along the way also highlights areas where cooperation from hardware will be needed in the future. cache) can be partitioned across domains; for those that are instead time-multiplexed, we have to flush them during domain switches. Threat scenarios.

Hardware 44

Hardware Cache Latency Speed 44

The Morning Paper

JUNE 25, 2019

This paper is all about the design of efficient data structures for far-memory, which turns out to have consequences reaching all the way down to the hardware. A far memory data structure has: far data in far memory, containing the core content of the data structure data caches at clients algorithms for operations. Refreshable vectors.

Design 80

Design Cache Hardware Scalability 80

SQL Performance

APRIL 27, 2020

Gen 5 is the primary hardware option now for most regions since Gen 4 is aging out. Hyperscale achieves high performance from each compute node having SSD-based caches which helps minimize the network round trips to fetch data. New Hardware Configuration for Provisioned Compute Tier. GB per vCore.

Azure 55

Azure Database Serverless Hardware 55

The Morning Paper

OCTOBER 4, 2020

Our analysis suggests that the wireline paths, upper-layer protocols, computing and radio hardward architecture need to co-evolve with 5G to form an ecosystem, in order to fully unleash its potential. This is a feature of the NSA architecture which requires dropping off of 5G onto 4G, doing a handover on 4G, and then upgrading to 5G again.

Energy 130

Energy Latency Performance Network 130

John McCalpin

AUGUST 1, 2018

According to Dr. Bandwidth, performance analysis has two recurring themes: How fast should this code (or “simple” variations on this code) run on this hardware? The user environment defines the mapping of MPI ranks to hardware resources (cores, sockets, nodes). The MPI runtime library. in ways that are seldom transparent.

Hardware 40

Hardware Transportation Performance Latency 40

Abhishek Tiwari

DECEMBER 27, 2017

In 2018, we anticipate that ETL will either lose relevance or the ETL process will disintegrate and be consumed by new data architectures. Unified data management architecture. Apache Arrow's in-memory columnar layout is specifically optimized for data locality for better performance on modern hardware like CPUs and GPUs.

Big Data 49

Big Data Artificial Intelligence Storage Hardware 49

SQL Performance

JULY 16, 2019

A close monitoring of the hardware enthusiast community, including many of the most respected hardware analysts and reviewers paints an even more dire picture about Intel in the server processor space. This made it easier for database professionals to make the case for a hardware upgrade, and made the typical upgrade more worthwhile.

Servers 46

Servers Hardware Architecture Retail 46

ACM Sigarch

NOVEMBER 1, 2019

This blog post gives a glimpse of the computer systems research papers presented at the USENIX Annual Technical Conference (ATC) 2019, with an emphasis on systems that use new hardware architectures. As a consequence, the vast majority of the papers in the past has usually focused on conventional X86 or GPU-accelerated architectures.

Architecture 12

Architecture Hardware Cache Storage 12

Sutter's Mill

FEBRUARY 13, 2017

.” This contains updated and new material that reflects the latest C++ standards and compilers, with a focus to using modern C++11/14/17 effectively on modern hardware and memory architectures. Note that the class size is limited to about 100, so that I’ll be able to interact with most attendees directly.

Latency 51

Latency C++ Hardware Performance 51

The Morning Paper

MAY 14, 2019

Last time around we looked at the DeathStarBench suite of microservices-based benchmark applications and learned that microservices systems can be especially latency sensitive, and that hotspots can propagate through a microservices architecture in interesting ways. When available, it can use hardware level performance counters.

Big Data 45

Big Data Cloud Performance Hardware 45

SQL Server According to Bob

JANUARY 11, 2020

Stable media is commonly physical disk storage, but other devices and certain caching facilities qualify as well. Many high-end disk subsystems provide high-speed cache facilities to reduce the latency of read and write operations. This cache is often supported by a battery-powered backup facility.

Servers 40

Servers Cache Media Hardware 40

John McCalpin

APRIL 25, 2023

For most high-end processors these values have remained in the range of 75% to 85% of the peak DRAM bandwidth of the system over the past 15-20 years — an amazing accomplishment given the increase in core count (with its associated cache coherence issues), number of DRAM channels, and ever-increasing pipelining of the DRAMs themselves.

Benchmarking 97

Benchmarking Cache Latency Tuning 97

Alex Russell

MARCH 6, 2021

A then-representative $200USD device had 4-8 slow (in-order, low-cache) cores, ~2GiB of RAM, and relatively slow MLC NAND flash storage. Hardware Past As Performance Prologue. Regardless, the overall story for hardware progress remains grim, particularly when we recall how long device replacement cycles are: Tap for a larger version.

Performance 124

Performance Network Cache Metrics 124

Brendan Gregg

FEBRUARY 28, 2023

Make sure your system can handle next-generation DRAM,” [link] , Nov 2011 [Hruska 12] Joel Hruska, “The future of CPU scaling: Exploring options on the cutting edge,” [link] , Feb 2012 [Gregg 13] Brendan Gregg, “Blazing Performance with Flame Graphs,” [link] , 2013 [Shimpi 13] Anand Lal Shimpi, “Seagate to Ship 5TB HDD in 2014 using Shingled Magnetic (..)

Performance 52

Performance Latency Cache Virtualization 52

Smashing Magazine

JANUARY 11, 2021

Defining The Environment Choosing a framework, baseline performance cost, Webpack, dependencies, CDN, front-end architecture, CSR, SSR, CSR + SSR, static rendering, prerendering, PRPL pattern. This improves page load time and caching during navigations. From Fast By Default: Modern loading best practices by Addy Osmani (Slide 19).

Performance 145

Performance Cache Media Metrics 145

CSS - Tricks

JULY 25, 2019

Cache-Headers missing? If you’re interested in a high-level overview of Lighthouse architecture, read this guide from the official repository. Service workers that will cache the bytecode result of a parsed and compiled script. After that, it’ll be mitigated by cache. What changed in PageSpeed 5.0?

Google 71

Google Engineering Speed Mobile 71

Highly Scalable

APRIL 2, 2012

From the business logic point of view, this was a pretty typical eCommerce service for hierarchical and faceted navigation, although not without peculiarities, but high performance requirements led us to the quite advanced architecture and technical design. So, the only way was to cache all necessary data to minimize interaction with RDBMS.

Ecommerce 100

Ecommerce Cache Storage Architecture 100

Smashing Magazine

JANUARY 6, 2020

On the other hand, we have hardware constraints on memory and CPU due to JavaScript parsing times (we’ll talk about them in detail later). Still, after all these years, keeping progressive enhancement as the guiding principle of your front-end architecture and deployment is a safe bet. Use progressive enhancement as a default.

Performance 145

Performance Cache Network Metrics 145

KeyCDN

JANUARY 23, 2020

A wide range of users with different operating systems, browsers, hardware configurations and other variables provides a wide sample size that helps developers discover as many issues as possible. Teams can measure the performance of all application dependencies, including databases, web services, caching, and more. Usage performance.

Strategy 72

Strategy Metrics Monitoring Servers 72

John McCalpin

NOVEMBER 5, 2016

The art and science of microprocessor architecture is a never-ending struggling to balance complexity, verifiability, usability, expressiveness, compactness, ease of encoding/decoding, energy consumption, backwards compatibility, forwards compatibility, and other factors.

Cache 40

Cache C++ Latency Hardware 40

Percona

APRIL 17, 2023

The swap issue is explained in the excellent article by Jeremy Cole at the Swap Insanity and NUMA Architecture. Make sure the drives are mounted with noatime and also if the drives are behind a RAID controller with appropriate battery-backed cache. There is an issue with this, which causes the OS to swap even with memory available.

Best Practices 52

Best Practices Design Tuning Database 52

Smashing Magazine

JANUARY 7, 2019

On the other hand, we have hardware constraints on memory and CPU due to JavaScript parsing times (we’ll talk about them in detail later). Keeping progressive enhancement as the guiding principle of your front-end architecture and deployment is a safe bet. Consider using PRPL pattern and app shell architecture.

Performance 103

Performance Cache Metrics Network 103

ACM Sigarch

NOVEMBER 4, 2019

The technical program, put together by program chairs Tor Aamodt and Reetuparna Das , showcased key innovations across a wide range of computer architecture topics, from domain-specific accelerators to in/near-memory computing and from security to quantum computing. . This year’s MICRO had three inspiring keynote talks.

Hardware 18

Hardware Architecture Programming Innovation 18

ScaleOut Software

JULY 27, 2018

Looking beyond distributed caching, it’s their ability to perform data-parallel analysis that gives IMDGs such exciting capabilities. Application developers often deploy IMDGs as a distributed cache that sits between an application and its database; the IMDG offloads ephemeral data from the database.

Scalability 40

Scalability Cache Airlines Healthcare 40