The Netflix TechBlog

JUNE 4, 2019

Because microprocessors are so fast, computer architecture design has evolved towards adding various levels of caching between compute units and the main memory, in order to hide the latency of bringing the bits to the brains. This avoids thrashing caches too much for B and evens out the pressure on the L3 caches of the machine.

Cache 251

Cache Latency Airlines Logistics 251

ACM Sigarch

MAY 31, 2023

Introduction Memory systems are evolving into heterogeneous and composable architectures. Heterogeneous and Composable Memory (HCM) offers a feasible solution for terabyte- or petabyte-scale systems, addressing the performance and efficiency demands of emerging big-data applications.

Latency 52

Latency Hardware Cache Architecture 52

The Morning Paper

JUNE 25, 2019

Designing far memory data structures: think outside the box Aguilera et al., Last time out we looked at some of the trade-offs between RInKs and LInKs , and the advantages of local in-memory data structures. For many data center applications this looks to me like it could be a compelling future choice. HotOS’19.

Design 80

Design Cache Hardware Scalability 80

Percona

JUNE 22, 2023

To make data count and to ensure cloud computing is unabated, companies and organizations must have highly available databases. Fault tolerance aims for zero downtime and data loss. Data replication : Data is continually copied from one database to another to ensure that the system remains operational even if one database fails.

Availability 105

Availability Database Open Source Hardware 105

ACM Sigarch

FEBRUARY 23, 2018

Engineers, like economists, deal with large amounts of data and pride ourselves on our clinical ability to analyze and solve complex problems. I had a professor in grad school who used to joke that all architecture is reinvented every 5 years. We believed existing hardware and OS protocols protected the processor.

Architecture 47

Architecture Cache Hardware Virtualization 47

Scalegrid

DECEMBER 21, 2023

In today’s data-driven world, the ability to effectively monitor and manage data is of paramount importance. Redis®, a powerful in-memory data store, is no exception. With its widespread use in modern application architectures, understanding the ins and outs of Redis® monitoring is essential for any tech professional.

Strategy 130

Strategy Monitoring Latency DevOps 130

Percona

APRIL 17, 2023

We’ll also go over some best practices for MongoDB security as well as MongoDB data modeling. The swap issue is explained in the excellent article by Jeremy Cole at the Swap Insanity and NUMA Architecture. There is an issue with this, which causes the OS to swap even with memory available. For example: $ /opt/mongodb/4.0.6/bin/mongos

Best Practices 52

Best Practices Design Tuning Database 52

The Morning Paper

MAY 12, 2019

An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems Gan et al., A typical architecture diagram for one of these services looks like this: Suitably armed with a set of benchmark microservices applications, the investigation can begin! Hardware implications.

Open Source 61

Open Source Hardware Benchmarking Systems 61

Abhishek Tiwari

DECEMBER 27, 2017

ETL refers to extract, transform, load and it is generally used for data warehousing and data integration. There are several emerging data trends that will define the future of ETL in 2018. A common theme across all these trends is to remove the complexity by simplifying data management as a whole.

Big Data 49

Big Data Artificial Intelligence Storage Hardware 49

The Morning Paper

MARCH 8, 2020

This paper describes the design decisions behind the Snowflake cloud-based data warehouse. This paper presents Snowflake design and implementation along with a discussion on how recent changes in cloud infrastructure (emerging hardware, fine-grained billing, etc.) From shared-nothing to disaggregation. joins) during query processing.

Storage 112

Storage Engineering Cache Serverless 112

High Scalability

NOVEMBER 25, 2019

There are a couple of downsides though in case you are looking to use it to support tens of thousands of users working on hundreds of millions of files simultaneously containing petabytes of data. To help our customers manage ongoing data explosion, we have designed many of the core components over the last few years. Edge caching.

Architecture 52

Architecture Cache Azure Storage 52

ACM Sigarch

OCTOBER 12, 2020

The focus of most published research in architecture is on applications implemented in high-performance, “ close-to-the-metal” languages essentially developed before computers got fast. Are caches large enough for this code? There’s some work on hardware proposals for these systems, like Zhu et al.,

C++ 108

C++ Benchmarking Hardware Architecture 108

ACM Sigarch

JULY 17, 2023

An example of a specification is the correct operation of the hardware of a microprocessor. If the fault is read but goes undetected, the outcome could be Silent Data Corruption (SDC). An SDC is the worst possible outcome of a fault, as it can have an arbitrary impact on the correctness of software running on the hardware.

Energy 52

Energy Hardware Best Practices Architecture 52

The Morning Paper

MAY 14, 2019

Seer: leveraging big data to navigate the complexity of performance debugging in cloud microservices Gan et al., When a QoS violation is predicted to occur and a culprit microservice located, Seer uses a lower level tracing infrastructure with hardware monitoring primitives to identify the reason behind the QoS violation.

Big Data 45

Big Data Cloud Performance Hardware 45

The Morning Paper

APRIL 14, 2019

The paper sets out what we can do in software given today’s hardware, and along the way also highlights areas where cooperation from hardware will be needed in the future. cache) can be partitioned across domains; for those that are instead time-multiplexed, we have to flush them during domain switches. Threat scenarios.

Hardware 44

Hardware Cache Latency Speed 44

Highly Scalable

AUGUST 20, 2013

The shortcomings and drawbacks of batch-oriented data processing were widely recognized by the Big Data community quite a long time ago. This system has been designed to supplement and succeed the existing Hadoop-based system that had too high latency of data processing and too high maintenance costs.

Big Data 154

Big Data Processing Lambda Database 154

Brendan Gregg

FEBRUARY 28, 2023

Make sure your system can handle next-generation DRAM,” [link] Nov 2011 - [Hruska 12] Joel Hruska, “The future of CPU scaling: Exploring options on the cutting edge,” [link] Feb 2012 - [Gregg 13] Brendan Gregg, “Blazing Performance with Flame Graphs,” [link] 2013 - [Shimpi 13] Anand Lal Shimpi, “Seagate to Ship 5TB HDD in 2014 using Shingled Magnetic (..)

Performance 110

Performance Latency Cache Virtualization 110

SQL Performance

APRIL 27, 2020

Many of the newer features we have in SQL Server were initially launched in Azure SQL Database, including (but not limited to) Always Encrypted, Dynamic Data Masking, Row Level Security, and Query Store. Gen 5 is the primary hardware option now for most regions since Gen 4 is aging out. DTU Pricing Tier. GB per vCore.

Azure 55

Azure Database Serverless Hardware 55

ScaleOut Software

JULY 27, 2018

For more than a decade, in-memory data grids (IMDGs) have proven their usefulness for storing fast-changing data in enterprise applications. Whether it’s ecommerce shopping carts, financial trading data, IoT telemetry, or airline reservations, these data sets need fast, reliable access for large, mission-critical workloads.

Scalability 40

Scalability Cache Airlines Healthcare 40

ScaleOut Software

JULY 27, 2018

For more than a decade, in-memory data grids (IMDGs) have proven their usefulness for storing fast-changing data in enterprise applications. Whether it’s ecommerce shopping carts, financial trading data, IoT telemetry, or airline reservations, these data sets need fast, reliable access for large, mission-critical workloads.

Scalability 40

Scalability Cache Airlines Healthcare 40

The Morning Paper

OCTOBER 4, 2020

As is expected to be common during the roll-out and transition phase of 5G, this network adopts the NSA (Non-Standalone Access) deployment model whereby the 5G radio is used for the data plane, but the control plane relies on existing 4G. Does 5G improve the end-user experience for applications (web browsing, and 4K+ video streaming)?

Energy 130

Energy Latency Performance Network 130

John McCalpin

APRIL 25, 2023

For most high-end processors these values have remained in the range of 75% to 85% of the peak DRAM bandwidth of the system over the past 15-20 years — an amazing accomplishment given the increase in core count (with its associated cache coherence issues), number of DRAM channels, and ever-increasing pipelining of the DRAMs themselves.

Benchmarking 97

Benchmarking Cache Latency Tuning 97

Smashing Magazine

JANUARY 11, 2021

Defining The Environment Choosing a framework, baseline performance cost, Webpack, dependencies, CDN, front-end architecture, CSR, SSR, CSR + SSR, static rendering, prerendering, PRPL pattern. It will help you build up a company-tailored case study with real data.

Performance 145

Performance Cache Media Metrics 145

John McCalpin

AUGUST 1, 2018

According to Dr. Bandwidth, performance analysis has two recurring themes: How fast should this code (or “simple” variations on this code) run on this hardware? The user environment defines the mapping of MPI ranks to hardware resources (cores, sockets, nodes). The MPI runtime library. in ways that are seldom transparent.

Hardware 40

Hardware Transportation Performance Latency 40

SQL Server According to Bob

JANUARY 11, 2020

To ensure data integrity for our customers who are running SQL Server, it is important that I/O environments provide appropriate functionality. Atomicity A transaction must be an atomic unit of work; either all of its data modifications are performed or none of them are performed.

Servers 40

Servers Cache Media Hardware 40

Alex Russell

MARCH 6, 2021

A then-representative $200USD device had 4-8 slow (in-order, low-cache) cores, ~2GiB of RAM, and relatively slow MLC NAND flash storage. In 2016, Jio swept over the subcontinent like a monsoon dropping a torrent of 4G infrastructure and free data rather than rain. Hardware Past As Performance Prologue. The Moto G4 , for example.

Performance 124

Performance Network Cache Metrics 124

Highly Scalable

APRIL 2, 2012

From the business logic point of view, this was a pretty typical eCommerce service for hierarchical and faceted navigation, although not without peculiarities, but high performance requirements led us to the quite advanced architecture and technical design. So, the only way was to cache all necessary data to minimize interaction with RDBMS.

Ecommerce 100

Ecommerce Cache Storage Architecture 100

Sutter's Mill

FEBRUARY 13, 2017

.” This contains updated and new material that reflects the latest C++ standards and compilers, with a focus to using modern C++11/14/17 effectively on modern hardware and memory architectures. Note that the class size is limited to about 100, so that I’ll be able to interact with most attendees directly.

Latency 48

Latency C++ Hardware Performance 48

CSS - Tricks

JULY 25, 2019

Google wrote: Faster sites don’t just improve user experience; recent data shows that improving site speed also reduces operating costs. Cache-Headers missing? If you’re interested in a high-level overview of Lighthouse architecture, read this guide from the official repository. After that, it’ll be mitigated by cache.

Google 71

Google Engineering Speed Mobile 71

ACM Sigarch

NOVEMBER 1, 2019

This blog post gives a glimpse of the computer systems research papers presented at the USENIX Annual Technical Conference (ATC) 2019, with an emphasis on systems that use new hardware architectures. As a consequence, the vast majority of the papers in the past has usually focused on conventional X86 or GPU-accelerated architectures.

Architecture 12

Architecture Hardware Cache Storage 12

SQL Performance

JULY 16, 2019

A close monitoring of the hardware enthusiast community, including many of the most respected hardware analysts and reviewers paints an even more dire picture about Intel in the server processor space. This made it easier for database professionals to make the case for a hardware upgrade, and made the typical upgrade more worthwhile.

Servers 46

Servers Hardware Architecture Retail 46

Smashing Magazine

JANUARY 6, 2020

It will help you build up a company-tailored case study with real data. Furthermore, using data from case studies and experiments published on WPO Stats will help increase sensitivity for business about why performance matters, and what impact it has on user experience and business metrics. Large preview ). Large preview ).

Performance 145

Performance Cache Network Metrics 145

Brendan Gregg

FEBRUARY 28, 2023

Make sure your system can handle next-generation DRAM,” [link] , Nov 2011 [Hruska 12] Joel Hruska, “The future of CPU scaling: Exploring options on the cutting edge,” [link] , Feb 2012 [Gregg 13] Brendan Gregg, “Blazing Performance with Flame Graphs,” [link] , 2013 [Shimpi 13] Anand Lal Shimpi, “Seagate to Ship 5TB HDD in 2014 using Shingled Magnetic (..)

Performance 52

Performance Latency Cache Virtualization 52

KeyCDN

JANUARY 23, 2020

RUM gathers data from real life users to analyze application performance. A wide range of users with different operating systems, browsers, hardware configurations and other variables provides a wide sample size that helps developers discover as many issues as possible. What is real user monitoring (RUM)? Usage performance.

Strategy 72

Strategy Metrics Monitoring Servers 72

Smashing Magazine

JANUARY 7, 2019

It will help you build up a company-tailored case study with real data. Furthermore, using data from case studies and experiments published on WPO Stats will help increase sensitivity for business about why performance matters, and what impact it has on user experience and business metrics.

Performance 104

Performance Cache Metrics Network 104

John McCalpin

NOVEMBER 5, 2016

The art and science of microprocessor architecture is a never-ending struggling to balance complexity, verifiability, usability, expressiveness, compactness, ease of encoding/decoding, energy consumption, backwards compatibility, forwards compatibility, and other factors. Optimization requires vectorization and data re-use.

Cache 40

Cache C++ Latency Hardware 40

ACM Sigarch

NOVEMBER 4, 2019

The technical program, put together by program chairs Tor Aamodt and Reetuparna Das , showcased key innovations across a wide range of computer architecture topics, from domain-specific accelerators to in/near-memory computing and from security to quantum computing. . This year’s MICRO had three inspiring keynote talks.

Hardware 18

Hardware Architecture Programming Innovation 18