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Achieving 100Gbps intrusion prevention on a single server

The Morning Paper

This makes the whole system latency sensitive. So we need low latency, but we also need very high throughput: A recurring theme in IDS/IPS literature is the gap between the workloads they need to handle and the capabilities of existing hardware/software implementations. The target FPGA for Pigasus has 16MB of BRAM.

Servers 128
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Seamless offloading of web app computations from mobile device to edge clouds via HTML5 Web Worker migration

The Morning Paper

Edge servers are the middle ground – more compute power than a mobile device, but with latency of just a few ms. These use their regression models to estimate processing time (which will depend on the hardware available, current load, etc.). Why would we want to live migrate web workers? for the wasm-version.

Mobile 104
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The Speed of Time

Brendan Gregg

A Cassandra database cluster had switched to Ubuntu and noticed write latency increased by over 30%. As a Xen guest, this profile was gathered using perf(1) and the kernel's software cpu-clock soft interrupts, not the hardware NMI. A quick check of basic performance statistics showed over 30% higher CPU consumption. us on Ubuntu.

Speed 126
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Boosted race trees for low energy classification

The Morning Paper

The goal is to produce a low-energy hardware classifier for embedded applications doing local processing of sensor data. The resulting system can integrate seamlessly into a scikit-learn based development process, and dramatically reduces the total energy usage required for classification with very low latency. Introducing race logic.

Energy 52
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Distributed Algorithms in NoSQL Databases

Highly Scalable

Historically, NoSQL paid a lot of attention to tradeoffs between consistency, fault-tolerance and performance to serve geographically distributed systems, low-latency or highly available applications. A database should accommodate itself to different data distributions, cluster topologies and hardware configurations. Data Placement.

Database 213
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A persistent problem: managing pointers in NVM

The Morning Paper

Byte-addressable non-volatile memory,) NVM will fundamentally change the way hardware interacts, the way operating systems are designed, and the way applications operate on data. Therefore any programming abstraction must be low latency and the kernel needs to be kept off the path of persistent data access as much as possible.

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A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing)

John McCalpin

Each of the two vector units can issue one FMA instruction per cycle, assuming that there are enough independent accumulators to tolerate the 6-cycle dependent-operation latency. This is an uninspiring fraction of peak performance that would normally suggest significant inefficiencies in either the hardware or software. jb.B1.8.

Latency 40