Distance-Based ISA for Efficient Register Management
ACM Sigarch
APRIL 2, 2025
Figure 1: Comparison of widest CPUs in 2015 and 2025. RISC-V is often considered a definitive RISC instruction set, as it was carefully designed to avoid past pitfalls, such as reliance on specific hardware characteristics (e.g., delay slots), which have limited the scalability of previous architectures.
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