Remove c
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Compress objects, not cache lines: an object-based compressed memory hierarchy

The Morning Paper

Compress objects, not cache lines: an object-based compressed memory hierarchy Tsai & Sanchez, ASPLOS’19. So while you probably won’t be using Zippads in practice anytime soon, it’s a wonderful example of what’s possible when you’re prepared to take a fresh look at “the way we’ve always done things.” Implications.

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WiredTiger Logging and Checkpoint Mechanism

Percona

” This acts as a step to ensure durability by recovering lost data from the same journal files in case of crashes, power, and hardware failures between the checkpoints (see below) Here’s what the process looks like. The same data, in the form of pages inside the Wiredtiger cache, are also marked dirty. wt and index-*.wt).

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Predictive CPU isolation of containers at Netflix

The Netflix TechBlog

Because microprocessors are so fast, computer architecture design has evolved towards adding various levels of caching between compute units and the main memory, in order to hide the latency of bringing the bits to the brains. This avoids thrashing caches too much for B and evens out the pressure on the L3 caches of the machine.

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From Heavy Metal to Irrational Exuberance

ACM Sigarch

These, let’s call them metal languages , include FORTRAN (introduced in 1957), C (1972), and C++ (1985). Programmers continue to write applications in them, and they continue to evolve: the just approved C++20 standard is the latest example. Are caches large enough for this code? As Leiserson et al.

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HammerDB for Managers

HammerDB

It enables the user to measure database performance and make comparative judgements about database hardware and software. These factors meant that often when looking for database performance information, the results for a particular combination of software and hardware were not available. What is HammerDB? Why HammerDB was developed.

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An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems

The Morning Paper

An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems Gan et al., The paper examines the implications of microservices at the hardware, OS and networking stack, cluster management, and application framework levels, as well as the impact of tail latency. ASPLOS’19.

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Seeing through hardware counters: a journey to threefold performance increase

The Netflix TechBlog

We also see much higher L1 cache activity combined with 4x higher count of MACHINE_CLEARS. a usage pattern occurring when 2 cores reading from / writing to unrelated variables that happen to share the same L1 cache line. Cache line is a concept similar to memory page?—? Thread 0’s cache in this example.

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