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The Speed of Time

Brendan Gregg

A Cassandra database cluster had switched to Ubuntu and noticed write latency increased by over 30%. Was there some other program consuming CPU, like a misbehaving Ubuntu service that wasn't in CentOS? I've shared many posts about superpower observability tools, but often humble hacking is just as effective. include <sys/time.h>

Speed 126
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The Speed of Time

Brendan Gregg

A Cassandra database cluster had switched to Ubuntu and noticed write latency increased by over 30%. Was there some other program consuming CPU, like a misbehaving Ubuntu service that wasn't in CentOS? I've shared many posts about superpower observability tools, but often humble hacking is just as effective. include <sys/time.h>

Speed 40
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The Performance Inequality Gap, 2024

Alex Russell

If you or your company are able to generate a credible worldwide latency estimate in the higher percentiles for next year's update, please get in touch. So what did $650, give or take, buy in late 2017 or early 2018? Front-end developers are cursed to program the Devil's computer. but which blessedly sports 8GB of RAM.

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AMD EPYC Processors in Azure Virtual Machines

SQL Performance

Back on December 5, 2017, Microsoft announced that they were using AMD EPYC 7551 processors in their storage-optimized Lv2-Series virtual machines. I wrote about using CPU-Z to benchmark the Intel Xeon E5-2673 v3 processor in an Azure VM in this article. Figure 1: CPU-Z Benchmark Results for LS16v2. Memory (GiB).

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Progress Delayed Is Progress Denied

Alex Russell

As an engineer on a browser team, I'm privy to the blow-by-blow of various performance projects, benchmark fire drills, and the ways performance marketing (deeply) impacts engineering priorities. With each team, benchmarks lost are understood as bugs. WebGL 2 launched for other platforms on Chrome and Firefox in 2017.

Media 145
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A peculiar throughput limitation on Intel’s Xeon Phi x200 (Knights Landing)

John McCalpin

Introduction: In December 2017, my colleague Damon McDougall (now at AMD) asked for help in porting the fused multiply-add example code from a Colfax report ( [link] ) to the Xeon Phi x200 (Knights Landing) processors here at TACC. simple addition instead of FMA) or with fewer registers and shorter pipeline latency (e.g,

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