Brendan Gregg

FEBRUARY 28, 2023

Make sure your system can handle next-generation DRAM,” [link] Nov 2011 - [Hruska 12] Joel Hruska, “The future of CPU scaling: Exploring options on the cutting edge,” [link] Feb 2012 - [Gregg 13] Brendan Gregg, “Blazing Performance with Flame Graphs,” [link] 2013 - [Shimpi 13] Anand Lal Shimpi, “Seagate to Ship 5TB HDD in 2014 using Shingled Magnetic (..)

Performance 110

Performance Latency Cache Virtualization 110

Brendan Gregg

FEBRUARY 28, 2023

Make sure your system can handle next-generation DRAM,” [link] , Nov 2011 [Hruska 12] Joel Hruska, “The future of CPU scaling: Exploring options on the cutting edge,” [link] , Feb 2012 [Gregg 13] Brendan Gregg, “Blazing Performance with Flame Graphs,” [link] , 2013 [Shimpi 13] Anand Lal Shimpi, “Seagate to Ship 5TB HDD in 2014 using Shingled Magnetic (..)

Performance 52

Performance Latency Cache Virtualization 52

Alex Russell

JUNE 19, 2020

Perhaps there's a better solution, but I've been iterating on content and templates by firing up a linux terminal on my 2017 Pixelbook and starting the built-in 11ty filewatcher and browser sync tools. Eleventy is I/O heavy, and for correctness sake, it didn't do much caching. Copied 1189 files / Wrote 1175 files in 5.75 MiB | 2.99

Cache 49

Cache Hardware Speed Cloud 49

ACM Sigarch

FEBRUARY 23, 2018

Richard Thaler won the 2017 Nobel prize in Economics for his work on Behavioral Economics. Hardware engineers design and implement solutions in RTL, while software engineers attempt to solve the problem either at the OS or application level. We believed existing hardware and OS protocols protected the processor.

Architecture 47

Architecture Cache Hardware Virtualization 47

SQL Server According to Bob

DECEMBER 18, 2018

Durability is a cornerstone of any database system and starting with SQL Server 2017 on Linux Cumulative Update 6 (CU6), SQL Server on Linux enables “Forced Flush” behavior as described in this article , improving durability on non-Fua optimized systems. “Be Linux open command flag used to bypass file system cache. Device Flush.

Servers 90

Servers Media Cache Storage 90

Sutter's Mill

FEBRUARY 13, 2017

” This contains updated and new material that reflects the latest C++ standards and compilers, with a focus to using modern C++11/14/17 effectively on modern hardware and memory architectures. On April 25-27, I’ll be in Stockholm (Kista) giving a three-day seminar on “High-Performance and Low-Latency C++.”

Latency 51

Latency C++ Hardware Performance 51

Alex Russell

MARCH 6, 2021

TL;DR: A lot has changed since 2017 when we last estimated a global baseline resource per-page resource budget of 130-170KiB. A then-representative $200USD device had 4-8 slow (in-order, low-cache) cores, ~2GiB of RAM, and relatively slow MLC NAND flash storage. Hardware Past As Performance Prologue. The Moto G4 , for example.

Performance 124

Performance Network Cache Metrics 124