ACM Sigarch

OCTOBER 12, 2020

The focus of most published research in architecture is on applications implemented in high-performance, “ close-to-the-metal” languages essentially developed before computers got fast. First, its origin was in a monoculture (the browser) wher e there was no need for compatibility with legacy code. MICRO 15 , Gope et al.,

C++ 108

C++ Benchmarking Hardware Architecture 108

Percona

JUNE 22, 2023

Defining high availability In general terms, high availability refers to the continuous operation of a system with little to no interruption to end users in the event of hardware or software failures, power outages, or other disruptions. If a primary server fails, a backup server can take over and continue to serve requests.

Availability 107

Availability Database Open Source Hardware 107

Highly Scalable

AUGUST 20, 2013

The whole point of this section is that all the algorithms above can be naturally implemented using a message passing architectural style i.e. the query execution engine can be considered as a distributed network of nodes connected by the messaging queues. Marz, “Big Data Lambda Architecture”. Jacobsen and R. Lyons, “The Sliding DFT“.

Big Data 154

Big Data Processing Lambda Database 154

The Morning Paper

MAY 12, 2019

An open-source benchmark suite for microservices and their hardware-software implications for cloud & edge systems Gan et al., A typical architecture diagram for one of these services looks like this: Suitably armed with a set of benchmark microservices applications, the investigation can begin! Hardware implications.

Open Source 61

Open Source Hardware Benchmarking Systems 61

ACM Sigarch

JULY 17, 2023

An example of a specification is the correct operation of the hardware of a microprocessor. An example protection technique that can provide this capability is an Error Correcting Code (ECC). An SDC is the worst possible outcome of a fault, as it can have an arbitrary impact on the correctness of software running on the hardware.

Energy 52

Energy Hardware Best Practices Architecture 52

The Morning Paper

APRIL 14, 2019

The paper sets out what we can do in software given today’s hardware, and along the way also highlights areas where cooperation from hardware will be needed in the future. Microarchitectural channels. There are also stateless interconnects including buses and on-chip networks. Threat scenarios. IPC) input and output channels.

Hardware 44

Hardware Cache Latency Speed 44

All Things Distributed

JULY 14, 2015

In this blog post, I will explain how these three new capabilities empower you to build applications with distributed systems architecture and create responsive, reliable, and high-performance applications using DynamoDB that work at any scale. At launch, an item’s change record is available in the stream for 24 hours after it is created.

Database 167

Database Lambda AWS IoT 167

John McCalpin

AUGUST 1, 2018

Bandwidth, performance analysis has two recurring themes: How fast should this code (or “simple” variations on this code) run on this hardware? Interacting components in the execution of an MPI job — a brief outline (from memory): The user source code, which contains an ordered set of calls to MPI routines.

Hardware 40

Hardware Transportation Performance Latency 40

Sutter's Mill

FEBRUARY 13, 2017

.” This contains updated and new material that reflects the latest C++ standards and compilers, with a focus to using modern C++11/14/17 effectively on modern hardware and memory architectures. Note that the class size is limited to about 100, so that I’ll be able to interact with most attendees directly.

Latency 51

Latency C++ Hardware Performance 51

SQL Server According to Bob

JANUARY 11, 2020

Stable media is commonly physical disk storage, but other devices and certain caching facilities qualify as well. Many high-end disk subsystems provide high-speed cache facilities to reduce the latency of read and write operations. This cache is often supported by a battery-powered backup facility.

Servers 40

Servers Cache Media Hardware 40

John McCalpin

NOVEMBER 5, 2016

The art and science of microprocessor architecture is a never-ending struggling to balance complexity, verifiability, usability, expressiveness, compactness, ease of encoding/decoding, energy consumption, backwards compatibility, forwards compatibility, and other factors. This includes Haswell and newer cores.

Cache 40

Cache C++ Latency Hardware 40

Alex Russell

OCTOBER 22, 2017

One distinct trend is a belief that a JavaScript framework and Single-Page Architecture (SPA) is a must for PWA development. Therefore, while a 150KB image won’t appreciably increase TTI, 150KB of JS will delay interactivity by the time required to: Request the code, including DNS, TCP, HTTP, and decompression overhead.

Performance 68

Performance Benchmarking Network Mobile 68

ScaleOut Software

JULY 27, 2018

Looking beyond distributed caching, it’s their ability to perform data-parallel analysis that gives IMDGs such exciting capabilities. Application developers often deploy IMDGs as a distributed cache that sits between an application and its database; the IMDG offloads ephemeral data from the database.

Scalability 40

Scalability Cache Airlines Healthcare 40

ScaleOut Software

JULY 27, 2018

Looking beyond distributed caching, it’s their ability to perform data-parallel analysis that gives IMDGs such exciting capabilities. Application developers often deploy IMDGs as a distributed cache that sits between an application and its database; the IMDG offloads ephemeral data from the database.

Scalability 40

Scalability Cache Airlines Healthcare 40

SQL Performance

MARCH 8, 2021

This uses hardware, typically a crystal oscillator, that produces ticks at a very high constant rate regardless of processor speed, power settings, or anything of that nature. Total elapsed time is 933ms with 6,673ms of CPU time with a warm cache. SQL Server uses the high-precision QueryPerformanceCounter API to capture timing data.

Servers 95

Servers Tuning Architecture Processing 95

Smashing Magazine

JANUARY 11, 2021

Have we optimized enough with tree-shaking, scope hoisting, code-splitting, and all the fancy loading patterns with intersection observer, progressive hydration, clients hints, HTTP/3, service workers and — oh my — edge workers? It’s much easier to reach performance goals when the code base is fresh or is just being refactored.

Performance 145

Performance Cache Media Metrics 145

Smashing Magazine

JANUARY 6, 2020

Is it worth exploring tree-shaking, scope hoisting, code-splitting, and all the fancy loading patterns with intersection observer, server push, clients hints, HTTP/2, service workers and — oh my — edge workers? It’s much easier to reach performance goals when the code base is fresh or is just being refactored.

Performance 145

Performance Cache Network Metrics 145

High Scalability

NOVEMBER 25, 2019

Over time, costs for S3 and GCS became reasonable and with Egnyte’s storage plugin architecture, our customers can now bring in any storage backend of their choice. Edge caching. In general, Egnyte connect architecture shards and caches data at different levels based on: Amount of data. Nginx for disk based caching.

Architecture 52

Architecture Cache Azure Storage 52

Smashing Magazine

JANUARY 7, 2019

Is it worth exploring tree-shaking, scope hoisting, code-splitting, and all the fancy loading patterns with intersection observer, server push, clients hints, HTTP/2, service workers and — oh my — edge workers? Keeping progressive enhancement as the guiding principle of your front-end architecture and deployment is a safe bet.

Performance 104

Performance Cache Network Metrics 104

John McCalpin

APRIL 25, 2023

For most high-end processors these values have remained in the range of 75% to 85% of the peak DRAM bandwidth of the system over the past 15-20 years — an amazing accomplishment given the increase in core count (with its associated cache coherence issues), number of DRAM channels, and ever-increasing pipelining of the DRAMs themselves.

Benchmarking 97

Benchmarking Cache Latency Tuning 97