Dynatrace

FEBRUARY 4, 2021

Site reliability engineering (SRE) is the practice of applying software engineering principles to operations and infrastructure processes to help organizations create highly reliable and scalable software systems. Shift-left using an SRE approach means that reliability is baked into each process, app and code change.

Engineering 246

Engineering DevOps Government Latency 246

Dynatrace

FEBRUARY 4, 2021

Site reliability engineering (SRE) is the practice of applying software engineering principles to operations and infrastructure processes to help organizations create highly reliable and scalable software systems. Shift-left using an SRE approach means that reliability is baked into each process, app and code change.

Engineering 167

Engineering DevOps Government Latency 167

Adrian Cockcroft

JANUARY 20, 2023

switches to connect processing nodes, pooled memory and I/O resources into very large coherent fabrics within a rack, and use Ethernet between racks. I have always been particularly interested in the interconnects and protocols used to create clusters, and the latency and bandwidth of the various offerings that are available.

Architecture 52

Architecture Latency Benchmarking AWS 52

The Morning Paper

JUNE 23, 2019

Factor VI in the 12-factor app manifesto , “Execute the app as one or more stateless processes,” to be dropped and replaced with “Execute the app as one or more stateful processes.” session state that you want to survive an application process crash), and to keep the application server/services layer stateless.

Cache 79

Cache Latency Google Lambda 79

HammerDB

OCTOBER 8, 2018

maximum transition latency: Cannot determine or is not supported. Latency: 0. postgres 201541 201539 0 Sep19 ? 00:00:57 postgres: checkpointer process. postgres 201542 201539 0 Sep19 ? 00:00:02 postgres: writer process. Copyright (C) 2003-2018 Steve Shaw. /cpupower frequency-info.

Best Practices 40

Best Practices Scalability Performance Hardware 40

HammerDB

OCTOBER 12, 2018

maximum transition latency: Cannot determine or is not supported. . Copyright (C) 2003-2018 Steve Shaw. Copyright (C) 2003-2018 Steve Shaw. Fortunately HammerDB allows all of this process to be automated. /cpupower frequency-info analyzing CPU 0: . CPUs which need to have their frequency coordinated by software: 0 .

Best Practices 40

Best Practices Scalability Performance C++ 40

O'Reilly Software

MARCH 7, 2018

Working with never-ending streams of data necessitates continuous processing of it, ensuring the system keeps up with the load patterns it is exposed to, and always provides real-time, up-to-date information. Sadly, it is very common to write logic that deeply couples the notion of IO with the processing of that IO.

Transportation 72

Transportation Java Programming Architecture 72