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Cache-Control for Civilians

CSS Wizardry

To this end, having a solid caching strategy can make all the difference for your visitors. ?? How is your knowledge of caching and Cache-Control headers? That being said, more and more often in my work I see lots of opportunities being left on the table through unconsidered or even completely overlooked caching practices.

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USENIX SREcon APAC 2022: Computing Performance: What's on the Horizon

Brendan Gregg

## References I've reproduced the references from my SREcon22 keynote below, so you can click on links: - [Gregg 08] Brendan Gregg, “ZFS L2ARC,” [link] Jul 2008 - [Gregg 10] Brendan Gregg, “Visualizations for Performance Analysis (and More),” [link] 2010 - [Greenberg 11] Marc Greenberg, “DDR4: Double the speed, double the latency?

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How It Works (It Just Runs Faster): Non-Volatile Memory SQL Server Tail Of Log Caching on NVDIMM

SQL Server According to Bob

Note: We received feedback that there was some confusion on us calling this functionality “tail of the log caching” because our documentation and prior history has referred to the tail of the log as the portion of the hardened log that has not been backed up. Block storage is what you think of today as disk access.

Cache 40
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USENIX SREcon APAC 2022: Computing Performance: What's on the Horizon

Brendan Gregg

References I've reproduced the references from my SREcon22 keynote below, so you can click on links: [Gregg 08] Brendan Gregg, “ZFS L2ARC,” [link] , Jul 2008 [Gregg 10] Brendan Gregg, “Visualizations for Performance Analysis (and More),” [link] , 2010 [Greenberg 11] Marc Greenberg, “DDR4: Double the speed, double the latency?

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The Performance Inequality Gap, 2021

Alex Russell

Back in 2016, I gave a talk outlining the causes and effects of the terrible performance of web apps built using popular tools on the fastest-growing device segment: low-end to mid-range Android phones. A then-representative $200USD device had 4-8 slow (in-order, low-cache) cores, ~2GiB of RAM, and relatively slow MLC NAND flash storage.

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AMD EPYC Processors in Azure Virtual Machines

SQL Performance

Back on December 5, 2017, Microsoft announced that they were using AMD EPYC 7551 processors in their storage-optimized Lv2-Series virtual machines. This processor has a base clock speed of 2.0GHz, with an all-core boost speed of 2.55GHz, and a max boost clock speed of 3.0GHz. The L3 cache size is 64MB.

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Can You Afford It?: Real-world Web Performance Budgets

Alex Russell

JavaScript is the single most expensive part of any page in ways that are a function of both network capacity and device speed. Add onto that the yawning chasm between low-end and high-end device performance thanks to chip design factors like cache sizes, and it can be difficult to know where to set a device baseline.