Brendan Gregg

AUGUST 29, 2021

Reads usually have apps waiting on them; writes may not (write-back caching). Hit Ctrl-C to end. ^C C msecs : count distribution 0 -> 1 : 83 | | 2 -> 3 : 20 | | 4 -> 7 : 0 | | 8 -> 15 : 41 | | 16 -> 31 : 1620 | * | 32 -> 63 : 8139 | *| 64 -> 127 : 176 | | 128 -> 255 : 95 | | 256 -> 511 : 61 | | 512 -> 1023 : 93 | |.

Cache 105

Cache C++ AWS Latency 105

Brendan Gregg

JULY 2, 2021

cachestat File system cache statistics line charts. Then, having discovered everything is C or Python, some rewrite it all in a different language. For a more recent example, I wrote cachestat(8) while on vacation in 2014 for use on the Netflix cloud, which was a mix of Linux 3.2 execsnoop New processes (via exec(2)) table.

Latency 145

Latency Cache Energy Systems 145

O'Reilly Software

JUNE 1, 2018

ccache, the compiler cache, is a fantastic way to speed up build times for C and C++ code that I previously recommended. Usually when this happens with ccache, there’s something non-deterministic about the builds that prevents cache hits.

Speed 40

Speed Cache C++ Code 40

Brendan Gregg

AUGUST 29, 2021

100.00 ^C I'm looking at the r_await column in particular: the average wait time for reads in milliseconds. Reads usually have apps waiting on them; writes may not (write-back caching). Hit Ctrl-C to end. ^C Hit Ctrl-C to end. ^C This is a 64-Gbyte memory system, and 48 Gbytes is in the page cache (the file system cache).

Cache 40

Cache C++ AWS Systems 40

Nick Desaulniers

JUNE 2, 2018

ccache , the compiler cache, is a fantastic way to speed up build times for C and C++ code that I previously recommended. Usually when this happens with ccache, there’s something non-deterministic about the builds that prevents cache hits. Cold Cache. kB max cache size 5.0 kB max cache size 5.0

Speed 46

Speed Cache C++ Systems 46

ACM Sigarch

MARCH 25, 2019

The M/M/1 queue will show us a required trade-off among (a) allowing unscheduled task arrivals, (b) minimizing latency, and (c) maximizing throughput. For the previous cache miss buffer example, the 32-buffer answer is minimal for 100-ns average miss latency. While Little’s Law provides a black-box result, it does not expose tradeoffs.

Systems 53

Systems Latency Performance C++ 53

ACM Sigarch

MARCH 18, 2019

For example, how many buffers must a cache have to record outstanding misses if it receives 2 memory references per cycle at 2.5 In our second blog post , we will present the M/M/1 queue that confronts us with a stark, required trade-off among (a) allowing unscheduled task arrivals, (b) minimizing latency, and (c) maximizing throughput.

Systems 60

Systems Latency Performance Analytics 60