Brendan Gregg

FEBRUARY 28, 2023

Titus, the Netflix container management platform, is now open source,” [link] Apr 2018 - [Cutress 19] Dr. DDR6: Here's What to Expect in RAM Modules,” [link] Nov 2020 - [Salter 20] Jim Salter, “Western Digital releases new 18TB, 20TB EAMR drives,” [link] Jul 2020 - [Spier 20] Martin Spier, Brendan Gregg, et al.,

Performance 110

Performance Latency Cache Virtualization 110

Brendan Gregg

JULY 2, 2021

cachestat File system cache statistics line charts. The architecture is: While the bpftrace binary is installed on all the target systems, the bpftrace tools (text files) live on a web server and are pushed out when needed. execsnoop New processes (via exec(2)) table. opensnoop Files opened table. ext4slower Slow filesystem I/O table.

Latency 145

Latency Cache Energy Systems 145

Brendan Gregg

FEBRUARY 28, 2023

Titus, the Netflix container management platform, is now open source,” [link] , Apr 2018 [Cutress 19] Dr. DDR6: Here's What to Expect in RAM Modules,” [link] , Nov 2020 [Salter 20] Jim Salter, “Western Digital releases new 18TB, 20TB EAMR drives,” [link] , Jul 2020 [Spier 20] Martin Spier, Brendan Gregg, et al.,

Performance 52

Performance Latency Cache Virtualization 52

Abhishek Tiwari

NOVEMBER 3, 2018

When it comes to innovation, most of CMS solutions are constrained by their legacy architecture (read strong coupling between content management and content presentation) which makes it difficult to serve content to new types of emerging channels such as apps and devices. Eventually, we decided to move them to Jekyll.

Systems 63

Systems Cache Website Network 63

Alex Russell

MARCH 6, 2021

A then-representative $200USD device had 4-8 slow (in-order, low-cache) cores, ~2GiB of RAM, and relatively slow MLC NAND flash storage. mid-priced Androids were slightly faster than 2014's iPhone 6. The Moto G4 , for example. The cheapest (high volume) Androids perform like 2012/2013 iPhones, respectively.

Performance 124

Performance Network Cache Metrics 124

ACM Sigarch

MARCH 18, 2019

For example, how many buffers must a cache have to record outstanding misses if it receives 2 memory references per cycle at 2.5 He is a fellow of IEEE and the ACM, serves as Chair of the Computer Community Consortium (2018-20) and served as Wisconsin Computer Sciences Department Chair 2014-17. Figure 2: (Sub-)System for Little’s Law.

Systems 60

Systems Latency Performance Analytics 60

ACM Sigarch

MARCH 25, 2019

For the previous cache miss buffer example, the 32-buffer answer is minimal for 100-ns average miss latency. He is a fellow of IEEE and the ACM, serves as Chair of the Computer Community Consortium (2018-20) and served as Wisconsin Computer Sciences Department Chair 2014-17. The M/M/1 design seems to over-designed by 2x (100ms ?

Systems 53

Systems Latency Performance C++ 53