Remove 2016 Remove Architecture Remove Cache Remove Speed
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USENIX SREcon APAC 2022: Computing Performance: What's on the Horizon

Brendan Gregg

## References I've reproduced the references from my SREcon22 keynote below, so you can click on links: - [Gregg 08] Brendan Gregg, “ZFS L2ARC,” [link] Jul 2008 - [Gregg 10] Brendan Gregg, “Visualizations for Performance Analysis (and More),” [link] 2010 - [Greenberg 11] Marc Greenberg, “DDR4: Double the speed, double the latency?

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USENIX SREcon APAC 2022: Computing Performance: What's on the Horizon

Brendan Gregg

References I've reproduced the references from my SREcon22 keynote below, so you can click on links: [Gregg 08] Brendan Gregg, “ZFS L2ARC,” [link] , Jul 2008 [Gregg 10] Brendan Gregg, “Visualizations for Performance Analysis (and More),” [link] , 2010 [Greenberg 11] Marc Greenberg, “DDR4: Double the speed, double the latency?

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The Performance Inequality Gap, 2021

Alex Russell

Back in 2016, I gave a talk outlining the causes and effects of the terrible performance of web apps built using popular tools on the fastest-growing device segment: low-end to mid-range Android phones. A then-representative $200USD device had 4-8 slow (in-order, low-cache) cores, ~2GiB of RAM, and relatively slow MLC NAND flash storage.

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The Performance Inequality Gap, 2023

Alex Russell

We're burning our inheritance and polluting the ecosystem on shockingly thin, perniciously marketed claims of "speed" and "agility" and "better UX" that have not panned out at all. That is, what was the average device in 2016? As this series has emphasised in years past, Average Selling Price ( ASP ) is destiny.

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The Surprising Effectiveness of Non-Overlapping, Sensitivity-Based Performance Models

John McCalpin

This was a keynote presentation at the “2nd International Workshop on Performance Modeling: Methods and Applications” (PMMA16), June 23, 2016, Frankfurt, Germany (in conjunction with ISC16 ). This includes all architectures, all compilers, all operating systems, and all system configurations.

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Is Intel Doomed in the Server CPU Space?

SQL Performance

From 2007 until 2016, Intel was able to successfully execute their Tick-Tock release strategy, where they would introduce a new processor microarchitecture roughly every two years (a Tock release). Intel has been stuck at 14nm in the server space since the Broadwell release in Q4 of 2016. So, what has changed my mind?

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Intel discloses “vector+SIMD” instructions for future processors

John McCalpin

The art and science of microprocessor architecture is a never-ending struggling to balance complexity, verifiability, usability, expressiveness, compactness, ease of encoding/decoding, energy consumption, backwards compatibility, forwards compatibility, and other factors.

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